The present invention relates to a false-synchronization detection device, particularly to which for a bit-synchronous circuit of a .pi./4-shift DQPSK (Differential Quaternary Phase Shift Keying) demodulator.
Description of the Related Art
For the purpose of providing a basic technological background with respect to the present invention, the description of a conventional art will be given with reference to FIGS. 1 and 2.
A structure of a conventional false-synchronization detection device which is applied to digital cellular phones etc., is illustrated in FIG. 1. In this particular device, a code comparison with respect to phase changes at former and latter halves of a symbol interval is conducted at a flip-flop 101 and an exclusive-OR (EX-OR) circuit 102 connected to both input and output terminals of the flip-flop 101. An output of the EX-OR circuit 102 is connected to an up-down terminal of a 4-bit up-down counter 103. Further, the up-down counter 103 is to carry out an up-down counting with an application of a signal, which is a regenerative symbol timing clock with a little delay being added, serving as a clock. At this time, when a value reaches zero from a predetermined original value, due to a down-counting, then the false-synchronization detection output is conducted.
In this respect, concerning a data pattern in which phases change in the same direction, a numerical value rises, by which a value does not reach zero even when down-counting happens due to false-synchronization. Further, flip-flops 104 and 105, and an OR circuit 106 are all used in initializing the up-down counter 103.
In this particular false-synchronization detection circuit, phase-change directions with respect to former and latter halves of a symbol interval are detected using a data pattern having phases of an opposite direction. Then when the former half and the latter half are changed in the opposite direction, it is determined that there is a false-synchronization. Moreover, such determination is not possible in a data pattern of a forward direction.
FIG. 2 is a diagram showing signal timing at each circuit constituent shown in FIG. 1. In this diagram, BTR indicates a regenerative clock which is to be inputted to the flip-flop 101, BAR indicates a regenerative symbol clock, BARD indicates a counter clock which is to be inputted to the up-down counter 103, ESYNC indicates an output of the EX-OR circuit 102, and U/D indicates an up-counting mode or a down-counting mode.
With respect to this conventional false-synchronization detection device, however, when there are consecutive forward data patters in which phases change in the same direction, the phase changes at the former half and the latter half become of the same codes even when the symbol timing is shifted. Thus the count value rises as described, by which count-down-offset is induced, rising difficulties in detecting any false-synchronization.